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82546gb dual port gigabit ethernet controller networking silicon datasheet product features ? pci/pci-x ? pci-x revision 1.0a support for frequencies up to 133 mhz ? multi-function pci device ? pci revision 2.3 support for 32-bit wide or 64-bit wide interface at 33 mhz and 66 mhz ? mac ? ieee 802.3x compliant flow control support with software controllable pause times and threshold values ? programmable host memory receive buffers (256 bytes to 16 kbytes) and cache line size (16 by tes to 256 bytes) ? wide, optimized internal data path architecture (128 bits) ? dual 64 kbytes configurable transmit and receive fifo buffers ? optimized descriptor fetching and write- back mechanisms ? phy ? integrated phy for 10/100/1000 mbps full and half duplex operation ? ieee 802.3ab auto-negotiation support ? ieee 802.3ab phy compliance and compatibility ? phy ability to automatically detect polarity and cable lengths and mdi versus mdi-x cable at all speeds ? host offloading ? transmit and receive ip, tcp and udp checksum off-load ing capabilities ?transmit tcp segmentation ? ieee 802.1q vlan support with vlan tag insertion, stripping and packet filtering for up to 4096 vlan tags ? advanced packet filtering ? manageability ? manageability featur es on both ports: smb port, asf 1.0, acpi, wake on lan, and pxe ? compliance with pci power management 1.1 and acpi 2.0 register set compliant ? two complete gigabit ethernet connections in a single device ? eight activity and link indication outputs that directly drive leds ? lead-free a 364-pin ball grid array (bga). devices that are lead-f ree are marked with a circled ?e1? and have the product code: nhxxxxxx. a. this device is lead-free. that is, lead has not been intenti onally added, but lead may still exist as an impurity at <1000 pp m. the material declaration data sheet, which includes lead impu rity levels and the concentration of other restriction on haz- ardous substances (rohs)-banned materials, is available at: ftp://download.intel.com/design/packtech/material_content_ic_package.pdf#pagemode=bookmarks in addition, this device has been tested and conforms to the sa me parametric specifications as previous versions of the de- vice. for more information regarding lead-free products from intel corporation, contact your intel field sales representative. 322558-002 revision 1.9 october 2009
ii datasheet revision history revision date description 1.9 oct 2009 ? updated section 5.1, table 2. 1.8 aug 2009 ? updated section 5.2, table 3. 1.7 oct 2005 ? changed interrupt signals inta# and intb# symbol types from ts (tri- state) to od (open drain). 1.6 june 2005 ? added a more detailed aux_pwr pin description. ? added tristate and xor non-jtag test modes description. 1.5 april 2005 ? added lead-free product and ordering information. ? added major product features to cover page. ? added text stating that the ttl inputs on the ethernet controller are not 5v tolerant. ? updated thermal specifications. 1.4 sept 2004 corrected the nominal impedance values for the i/o cells from 50 k ? to a nominal impedance value of 120 k ? , with a minimum of 90 k ? and a maximum of 190 k ? . 1.3 dec 2003 added an i/o characteristics tabl e in section 4.3, ?dc characteristics.? 1.2 nov 2003 corrected typing error of ?q? to ? ? ? in section 6.3, ?thermal specifications,? on page 38 . 1.1 sept 2003 declassified document from confidential status. 1.0 july 2003 initial release. information in this document is provided in connection with inte l products. no license, express or implied, by estoppel or othe rwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, inte l assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liabil ity or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property righ t. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and pr oduct descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instruct ions marked "reserved" or "undefined." int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the 82546gb gigabit ethernet controller may contain design defects or errors known as errata which may cause the product to dev iate from published specifications. current characte rized errata are available on request. contact your local intel sales office or your distributor to obt ain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are refer enced in this document, or other intel literature may be obtaine d by calling 1-800- 548-4725 or by visiting intel's website at http://www.intel.com. copyright ? 2009, intel corporation. intel ? is a trademark or registered trademark of intel corporati on or its subsidiaries in the united states and other countries. *third-party brands and names are the property of their respective owners.
datasheet iii networking silicon ? 82546gb contents 1.0 introduction................................................................................................................ ......... 1 1.1 document scope................................................................................................... 2 1.2 reference documents........................................................................................... 2 1.3 product codes....................................................................................................... 3 2.0 additional 82546gb features ............................................................................................ 5 2.1 pci ........................................................................................................................ 5 2.2 mac ...................................................................................................................... 5 2.3 phy ....................................................................................................................... 5 2.4 host offloading...................................................................................................... 6 2.5 manageability ........................................................................................................ 6 2.6 device ................................................................................................................... 7 2.7 technology............................................................................................................ 7 3.0 signal descriptions......................................................................................................... ....8 3.1 signal type definitions.......................................................................................... 8 3.2 pci bus interface .................................................................................................. 8 3.2.1 pci address, data and control signals ................................................... 9 3.2.2 arbitration signals .................................................................................. 10 3.2.3 interrupt signals ..................................................................................... 10 3.2.4 system signals....................................................................................... 11 3.2.5 error reporting signals ................ .......................................................... 11 3.2.6 power management signals .................................................................. 11 3.2.7 impedance compensation signals......................................................... 12 3.2.8 smb signals........................................................................................... 12 3.3 eeprom interface signals ................. ................ ............. ............. ............ .......... 12 3.4 flash interface signals........................ ................................................................ 13 3.5 miscellaneous signals......................................................................................... 13 3.5.1 led signals............................................................................................ 13 3.5.2 software definable signals .................................................................... 13 3.6 phy signals ........................................................................................................ 14 3.6.1 crystal signals ....................................................................................... 14 3.6.2 phy analog signals ............................................................................... 14 3.7 serializer / deserializer signals........... ................................................................ 15 3.8 jtag test interface signals ............... ................................................................ 16 3.9 power supply connections ................................................................................. 16 3.9.1 power support signals........................................................................... 16 3.9.2 digital supplies....................................................................................... 16 3.9.3 analog supplies ..................................................................................... 16 3.9.4 ground and no connects....................................................................... 17 4.0 test port functionality..................................................................................................... .18 4.1 xor testing........................................................................................................ 18 4.1.1 xor tree control and operation........................................................... 18 4.1.2 pins tested ............................................................................................ 19 4.2 tristate mode ...................................................................................................... 20 4.2.1 tristate mode control and operatio n ..................................................... 20
82546gb ? networking silicon iv datasheet 4.2.2 tristate mode using jtag (tap)........................................................... 20 5.0 voltage, temperature, and timing specifications ........................................................... 21 5.1 targeted absolute maximum ratings .... ............................................................. 21 5.2 recommended operating conditions ....... .......................................................... 21 5.3 dc specifications ................................................................................................ 22 5.4 ac characteristics .............................................................................................. 25 5.5 serial interface specifications ............................................................................. 26 5.6 timing specifications .......................................................................................... 27 5.6.1 pci/pci-x bus interface ........................................................................ 27 5.6.1.1 pci/pci-x bus interface clock.................................................. 27 5.6.1.2 pci/pci-x bus interface timing................................................ 28 5.6.2 link interface timing .............................................................................. 30 5.6.2.1 link interface rise and fall time.............................................. 30 5.6.2.2 link interface transmit timi ng .................................................. 31 5.6.2.3 link interface receive timing ................................................... 32 5.6.3 flash interface ....................................................................................... 33 5.6.4 eeprom interface................................................................................. 34 6.0 package and pinout information ...................................................................................... 35 6.1 device identification ........................................................................................... 35 6.2 package information ........................................................................................... 36 6.3 thermal specifications........................................................................................ 38 6.4 ball mapping diagram ............................ ............................................................. 39 6.5 pinout information ............................................................................................... 40 figures 1 gigabit ethernet controller block diagram ........................................................... 2 2 xor tree concept.............................................................................................. 18 3 ac test loads for general output pins.............................................................. 26 4 pci/pci-x clock timing ...................................................................................... 27 5 pci bus interface output timing measurement ................................................. 29 6 pci bus interface input timing measurement conditions .................................. 29 7 tval (max) rising edge test load.................................................................... 29 8 tval (max) falling edge test load ......... .......................................................... 30 9 link interface rise/fall timing ............................................................................ 31 10 transmit interface timing ................................................................................... 31 11 receive interface timing .................................................................................... 32 12 flash read timing .............................................................................................. 33 13 flash write timing .............................................................................................. 33 14 82546gb device identification markings ............................................................ 35 15 82546gb 364-lead bga ball pad dimensions .................................................. 36 16 82546gb mechanical specifications...... ............................................................. 37 tables 1 tested pins included in xor tree...................................................................... 19 2 absolute maximum ratings ................................................................................ 21 3 recommended operating conditions .......... ....................................................... 21 4 dc characteristics .............................................................................................. 22 5 power supply characteristics ............................................................................. 22
datasheet v networking silicon ? 82546gb 6 i/o characteristics............................................................................................... 24 7 ac characteristics: 3.3 v interfacing .................................................................. 25 8 25 mhz clock input requirements...................................................................... 25 9 link interface clock requirements ..................................................................... 25 10 eeprom interface clock requirements .. ................ ................ ................ .......... 26 11 ac test loads for genera l output pins.............................................................. 26 12 driver characteristics .......................... ................................................................ 26 13 receiver characteristics ..................................................................................... 27 14 pci/pci-x bus interface clock parameters ........................................................ 27 15 pci/pci-x bus interface timing parameters ...................................................... 28 13 pci bus interface timing measurement conditions ........................................... 28 16 rise and fall times............................................................................................. 30 17 transmit interface timing .................................................................................... 31 18 receive interface timing..................................................................................... 32 19 flash read operation timing ............................................................................. 33 20 flash write operation timing.............................................................................. 34 21 link interface clock requirements ..................................................................... 34 22 link interface clock requirements ..................................................................... 34 23 thermal characteristics ...................................................................................... 38 24 pci address, data, and control signals ............................................................. 40 25 pci arbitration signals ........................................................................................ 40 26 interrupt signals .................................................................................................. 41 27 system signals.................................................................................................... 41 28 error reporting signals ....................................................................................... 41 29 power management signals ............................................................................... 41 30 impedance compensation signals...................................................................... 41 31 smb signals........................................................................................................ 41 32 eeprom interface signals .... ................ ................ ................ ................ ............. 41 33 flash interface signals........................................................................................ 42 34 led signals......................................................................................................... 42 35 software definable signals .................... ............................................................. 42 36 crystal signals .................................................................................................... 42 37 phy signals ........................................................................................................ 42 38 serializer / deserializer signals........................................................................... 43 39 jtag test interface sign als ............................................................................... 43 40 power support signals........................................................................................ 43 41 digital power signals .......................................................................................... 44 42 analog power signals ......................................................................................... 44 43 grounds and no connect signals.......... ............................................................. 45 44 reserved signals ................................................................................................ 46
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networking silicon ? 82546gb datasheet 1 1.0 introduction the intel ? 82546gb dual port gigabit ethernet controller is a single, compact component with two full integrated gigabit ethernet media a ccess control (mac) and physical layer (phy) functions. the intel ? 82546gb enables dual port gigabit ethernet implementations in a very small area and can be used for desktop and worksta tion pc network designs as well as backplane applications with cr itical space constraints. the intel ? 82546gb integrates intel?s fourth generation gigabit mac and phy to provide a standard ieee 802.3 ethernet interface for 1000base-t, 100ba se-tx, and 10base-t applications (802.3, 802.3u, and 802.3ab). the controller is capable of transmitting and receiving two channels of data at rates of 1000 mbps, 100 m bps, or 10 mbps. in addition, it provides a 64-bit wide direct peripheral compone nt interconnect (pci) 2.3 and pci-x 1.0a compliant interface capable of operating at frequencies up to 133 mhz. the 82546gb also delivers a dual port pci-x solution without added bridge latency. the intel ? 82546gb on-board system management bus (smb) port enables network manageability implementations required by inform ation technology personnel for remote control and alerting through the lan. using the smb, management packets can be routed to or from a management processor. the smb port enables industry standards, such as intelligent platform management interface (ipmi) and alert standard format (asf), to be implemented using the 82546gb. in addition, on chip asf 1.0 circuitry provides alerting and remote control capabilities with standardized interfaces. the 82546gb dual port gigabit ethernet controller architecture is designed to deliver high performance and pci/pci-x bus efficiency. wide internal data paths eliminate performance bottlenecks by efficiently handling large address and data words. combining a parallel and pipe- lined logic architecture optimized for gigabit ethernet an d independent transmit and receive queues, the 82546gb controller efficiently handles packets with minimum latency. the 82546gb controller includes advanced interrupt handling f eatures to limit pci bus traffic and a pci interface that maximizes the use of bursts for efficient bus usage. the 82546gb is able to cache up to 64 packet descriptors in a single burst for efficient pci bandwidth use. a large 64 kbyte on-chip packet buffer maintains superi or performance as available pci bandwidth changes. by using hardware acceleration, the controller is able to offload tasks, such as checksum calculations and tcp segmentation, from the host processor.
82546gb ? networking silicon 2 datasheet the 82546gbis packaged in a 21 mm x 21 mm 364-ball grid array and footprint compatible with the intel ? 82544gc gigabit ethernet controller and 82546eb dual port gigabit ethernet controller. 1.1 document scope this document contains datasheet specifications for the 82546gb dual port gigabit ethernet controller, which includes signal descriptions, dc and ac parameters, packaging data, and pinout information. 1.2 reference documents it is assumed that the designer is acquainted with high-speed design and board layout techniques. document that may provide additional information are: ? pci local bus specification, revision 2.3, pci special interest group. ? pci-x specification, revision 1.0a, pci special interest group. ? pci bus power management interface specificatio n, rev. 1.1, pci special interest group. ? ieee standard 802.3, 1996 editio n, institute of electrical an d electronics engineers (ieee). ? ieee standard 802.3u, 1995 edition, institute of electrical and electroni cs engineers (ieee). ? ieee standard 802.3x, 1997 edition, institute of electrical and electroni cs engineers (ieee). ? ieee standard 802.3z, 1998 editio n, institute of electrical an d electronics engineers (ieee). figure 1. gigabit ethernet controller block diagram p ci (64 bit,33/66mhz); pc i -x (133mhz) s /w de f ined p ins m di i n te r face a d esi g n for tes t i nter f ace l ed's 1000base-t phy interfaces e eprom i nter f ace flash interface s m bus i nter f ace device funct. #0 mac/controller (lan a) 10/100/1000 phy m dio gmii/ m ii device funct. #1 mac/controller (lan b) 10/100/1000 phy m dio gmii/ m ii s /w de f ined p ins l ed's e xterna l tbi inter f ac e m di i nter f ace b
networking silicon ? 82546gb datasheet 3 ? ieee standard 802.3ab, 1999 edition, institu te of electrical and electronics engineers (ieee). ? intel ? ethernet controllers timing device sel ection guide, ap-419. intel corporation. 1.3 product codes the product ordering code for the 82546gb is: FW82546GB. the lead-free product ordering code for the 82546gb is: nh82546gb.
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networking silicon ? 82546gb datasheet 5 2.0 additional 82546gb features 2.1 pci 2.2 mac 2.3 phy feature benefits algorithms that optimally use advanced pci, mwi, mrm, and mrl commands as well as pci-x mrd, mrb, and mwb commands ? efficient bus operations features benefits low-latency transmit and receive queues ? network packets handled without waiting or buffer overflow. caches up to 64 packet descriptors in a single burst ? efficient use of pci bandwidth descriptor ring management hardware for transmit and receive ? simple software programming model mechanism available for reducing interrupts generated by transmit and receive operations ? maximizes system performance and throughput support for transmission and reception of packets up to 16 kbytes ? enables jumbo frames feature benefits state-of-the-art dsp architecture implements digital adaptive equalization, echo cancellation, and cross- talk cancellation ? robust performance in noisy environments ? tolerance of common electrical signal impairments
82546gb ? networking silicon 6 datasheet 2.4 host offloading 2.5 manageability features benefits descriptor ring management hardware for transmit and receive ? optimized fetching and write-back mechanisms for efficient system memory and pci bandwidth usage 16-kbyte jumbo frame support ? high throughput for large data transfers on networks supporting jumbo frames interrupt coalescing (multiple packets per interrupt) ? increased throughput by reducing interrupts generated by transmit and receive operations features benefits on-board smb port ? enables ipmi and asf implementations ? allows packets routing to and from either lan port and a server management processor preboot execution environment (pxe) flash interface support (32-bit and 64-bit) ? local flash interface for pxe image compliance with pci power management 1.1 and acpi 2.0 register set compliant including: ? d0 and d3 power states ? network device class power management specification 1.1 ? pci specification 2.3 ? pci power management capability requirements for pc and embedded applications snmp and rmon statistic counters ? easy system monitoring with industry standard consoles sdg 3.0, wfm 2.0, and pc2001 compliance ? remote network management capabilities through dmi 2.0 and snmp software wake on lan support ? packet recognition and wake-up for nic and lom applications without software configuration ipmi mac address read capability ? allows mac address read to be read by remote users through impi ipmi i 2 c addressing capability ? enables device addressing over the i 2 c bus
networking silicon ? 82546gb datasheet 7 2.6 device 2.7 technology features benefits internal pll for clock generation (use either a 25 mhz crystal or a 25 mhz oscillator) ? lower component count and system cost jtag (ieee 1149.1) test access port built in silicon ? simplified testing using boundary scan on-chip power control circuitry ? reduced number of on-board power supply regulators ? simplified power supply design eight software definable pins ? additional flexibility for leds or other low speed i/o devices supports little endian byte ordering for both 32 and 64 bit systems and big endian byte ordering for 64 bit systems ? portable across application architectures provides loopback capabilities ? validates silicon integrity single-pin lan disable function ? allows lan port enabling and disabling through bios control (os not required) for both ports vlan management filtering ? allows vlan-based management packet filtering full 2/3 wire downshift capability ? allows silicon to downshift speed to two or three wire install and stil l achieve valid link picmig 3.1 compliant serdes interface ? enables interface connec tions with picmig 3.1 compliant devices features benefits 364-pin ball grid array (bga) package ? 21 mm x 21 mm component makes lom designs easier footprint compatible with the 82544gc/ei and 82545gm/em single port gigabit ethernet controllers ? single port or dual port implementation on the same board with minor option changes. implemented in 0.15 cmos process ? offers lowest geometry to minimize power and size while maintaining intel quality reliability standards 3.3 v pci signaling with an average power dissipation of 3.5 w ? lower power requirements operating temperature: 0 c to 55 c (with or without thermal management, maximum); 0 c to 70 c (with increased thermal management, maximum) ? extended temperature attainable with thermal management device for more demanding systems requiring a wider temperature range.
82546gb ? networking silicon 8 datasheet 3.0 signal descriptions note: the targeted signal names are subject to change wi thout notice. verify with your local intel sales office that you have the latest info rmation before fina lizing a design. 3.1 signal type definitions the signals of the 82546gb controller are electrically defined as follows: note: the ttl inputs on the ethernet co ntroller are not 5v tolerant. if th ese inputs are connected to 5v, then damage to the ethernet controller is like ly to occur. ttl inputs include the jtag interface pins, the flash interface pins, th e eeprom interface pins, the le d pins, the software definable pins, and the lan_pwr_good pin. 3.2 pci bus interface when the reset signal (rst#) is asserted, the 82546gb will not drive any pci output or bi- directional pins except the power management event signal (pme#). name definition i input. standard input only digital signal. o output. standard output only digital signal. ts tri-state. bi-directional three-state digital input/output signal. sts sustained tri-state. sustained digital three-state signal driven by one agent at a time. an agent driving the sts pin low must actively dr ive it high for at least one clock before letting it float. the next agent of the signal cannot driv e the pin earlier than one clock after it has been released by the previous agent. od open drain. wired-or with other agents. the signaling agent asserts the od signal, but the signal is returned to the inactive state by a weak pull-up resistor. the pull-up resistor may r equire two or three clock periods to fully restore the signal to the de-asserted state. a analog. phy analog data signal. p power. power connection, voltage reference, or other reference connection. r reserved.
networking silicon ? 82546gb datasheet 9 3.2.1 pci address, data and control signals symbol type name and function ad[63:0] ts address and data. address and data signals are multiplexed on the same pci pins. a bus transaction includes an address phas e followed by one or more data phases. the address phase is the clock cycle when the frame signal (frame#) is asserted low. during the address phase ad[63:0] cont ain a physical address (64 bits). for i/o, this is a byte address, and for confi guration and memory, a dword address. the 82546gb device uses little endian byte ordering. during data phases, ad[7:0] contain the leas t significant byte (lsb) and ad[63:56] contain the most significant byte (msb). the 82546gbcontroller may optionally be connec ted to a 32-bit pci bus. on the 32-bit bus, ad[63:32] and other signals correspondi ng to the high order byte lanes do not participate in the bus cycle. cbe[7:0]# ts bus command and byte enables. bus command and byte enable signals are multiplexed on the same pci pins. during the address phase of a transaction, cbe[7:0]# define the bus command. in the data phase, cbe[7:0]# are used as byte enables. the byte enables are valid for the entire data phase and determine which byte lanes contain meaningful data. cbe0# applies to byte 0 (lsb) and cbe7# applies to byte 7 (msb). par ts parity. the parity signal is issued to implem ent even parity across ad[31:0] and cbe[3:0]#. par is stable and valid one clock after the address phase. during data phases, par is stable and valid one clock after either irdy# is asserted on a write transaction or trdy# is asserted after a read tr ansaction. once par is valid, it remains valid until one clock after the completion of the current data phase. when the 82546gb controller is a bus master , it drives par for address and write data phases, and as a slave device, dr ives par for read data phases. par64 ts parity 64. the parity 64 signal is issued to im plement even parity across ad[63:32] and cbe[7:4]#. par64 is stable and valid one clock after the address phase. during data phases, par64 is stable and valid one cloc k after either irdy# is asserted on a write transaction or trdy# is asserted after a read transaction. once par64 is valid, it remains valid until one clock after the completion of the current data phase. when the 82546gb controller is a bus master, it drives par64 for address and write data phases, and as a slave device, drives par64 for read data phases. frame# sts cycle frame. the frame signal is driven by the 82546gb device to indicate the beginning and length of an access and indi cate the beginning of a bus transaction. while frame# is asserted, data transfers continue. frame# is de-asserted when the transaction is in the final data phas e. irdy# sts initiator ready. initiator ready indicates the ability of the 82546gb controller (as bus master device) to complete the current data phase of the transaction. irdy# is used in conjunction with the target ready signal (trdy#). the data phase is completed on any clock when both irdy# and trdy# are asserted. during the write cycle, irdy# indicates that valid data is present on ad[63:0]. for a read cycle, it indicates the master is ready to accept data. wait cycles are inserted until both irdy# and trdy# are asserted together. the 82546gb controller drives irdy# when acting as a master and samples it when acting as a slave. trdy# sts target ready. the target ready signal indicates the ability of the 82546gb controller (as a selected device) to complete the current data phase of the transaction. trdy# is used in conjunction with the initiator ready signal (irdy#). a data phase is completed on any clock when both trdy# and irdy# are sampled asserted. during a read cycle, trdy# indicates that va lid data is present on ad[63:0]. for a write cycle, it indicates the target is ready to ac cept data. wait cycles are inserted until both irdy# and trdy# are asserted together. the 82546gb device drives trdy# when acting as a slave and samples it when acting as a master.
82546gb ? networking silicon 10 datasheet 3.2.2 arbitration signals 3.2.3 interrupt signals stop# sts stop. the stop signal indicates the current target is requesting the master to stop the current transaction. as a slave, the 82546 gb controller drives stop# to request the bus master to stop the transaction. as a master, the 82546gb controller receives stop# from the slave to stop the current transaction. idsel# i initialization device select. the initialization device se lect signal is used by the 82546gb as a chip select signal during c onfiguration read and write transactions. devsel# sts device select. when the device select signal is ac tively driven by the 82546gb, it signals notifies the bus master that it has decoded its address as the target of the current access. as an input, devsel# i ndicates whether any device on the bus has been selected. vio p vio. the vio signal is a voltage reference for the pci interface (3.3 v or 5 v pci signaling environment). it is used as the clamping voltage. note: an external resistor is required bet ween the voltage reference and the vio pin. the target resistor value is 100 k ? symbol type name and function req64# ts request transfer. the request transfer signal is generated by the current initiator indicating its desire to perform a 64-bit trans fer. req64# has the same timing as the frame signal. ack64# ts acknowledge transfer. the acknowledge transfer si gnal is generated by the currently addressed target in response to the req64# assertion by the initiator. ack64# has the same timing as the device select signal. req# ts request bus. the request bus signal is used to re quest control of the bus from the arbiter. this signal is point-to-point. gnt# i grant bus. the grant bus signal notifies the 82546gb that bus access has been granted. this is a point-to-point signal. lock# i lock bus. the lock bus signal is asserted by an initiator to require sole access to a target memory device during two or mo re separate transfers. the 82546gb device does not implement bus locking. symbol type name and function inta# od interrupt a. interrupt a is used to request an interrupt by port 1 of the 82546gb. it is an active low, level-triggered interrupt signal. intb# od interrupt b. interrupt b is used to request an interrupt by port 2 of the 82546gb. it is an active low, level-triggered interrupt signal. symbol type name and function
networking silicon ? 82546gb datasheet 11 3.2.4 system signals 3.2.5 error repo rting signals 3.2.6 power mana gement signals symbol type name and function clk i pci clock. t he pci clock signal provides timing for all transactions on the pci bus and is an input to the 82546gb device. all othe r pci signals, except the interrupt a (inta#) and pci reset signal (rst#), are sampled on the rising edge of clk. all other timing parameters are defined with respect to this edge. m66en i 66 mhz enable. t he 66 mhz enable signal is used to indicate whether or not the system bus is capable of supporti ng an operating frequency of 66 mhz. rst# i pci reset. when the pci reset signal is asserted, all pci output signals, except the power management event signal (pme#), are fl oated and all input signals are ignored. the pme# context is preserved, depending on power management settings. most of the internal state of the 82546gb is reset on the de-assertion (rising edge) of rst#. lan_ pwr_ good i power good (power-on reset). the power good signal is used to indicate that stable power is available for the 82546gb. when the signal is low, the 82546gb holds itself in reset state and floats all pci signals. symbol type name and function serr# od system error. the system error signal is used by the 82546gb controller to report address parity errors. serr# is open drain and is actively driven fo r a single pci clock when reporting the error. perr# sts parity error. the parity error signal is used by the 82546gb controller to report data parity errors during all pci transactions ex cept by a special cycle. perr# is sustained tri-state and must be driven active by the 82546gb controller two data clocks after a data parity error is detected. the minimu m duration of perr# is one clock for each data phase a data parity error is present. symbol type name and function pme# od power management event. the 82546gb device drives th is signal low when it receives a wake-up event and either the pme enable bit in the power management control/status register or the advanced power management enable (apme) bit of the wake-up control register (wuc) is 1b. aux_pwr i auxiliary power. if the auxiliary power signal is high , then auxiliary power is available and the 82546gb device should support the d3cold power state. note that aux_pwr is not a supply input, but is an indication of whether aux_pwr is available to the 82546gb and/or subsyst em. setting aux_pwr to 1b enables advertising d3cold wake up support and changes the reset function of pme_en and pme_status. aux_pwr is level sensitive, and any changes are i mmediately reflected in the d3cold wake up advertisements and the pme_en and pme_status behavior on pci reset.
82546gb ? networking silicon 12 datasheet 3.2.7 impedance compensation signals 3.2.8 smb signals note: a pull-up resistor with a recommended value of 4.7 k ? should be placed along the smb. a precise value may be calculated from the smb specification. 3.3 eeprom interface signals symbol type name and function zn_comp i/o n device impedance compensation. this signal should be c onnected to an external precision resistor (to vdd) that is indicative of the pci/pci -x trace load. this cell is used to dynamically determi ne the drive strength requir ed on the n-channel transistors in the pci/pci-x i/o cells. the internal pull-up imp edance is nominally 120 k ? with a minimum of 90 k ? and a maximum of 190 k ? . zp_comp i/o p device impedance compensation. this signal should be connected to an external precision resistor (to vss) that is indicative of the pci/pci-x trace load. this cell is used to dynamically determi ne the drive strength required on the p-channel transistors in the pci/pci-x i/o cells. the internal pull-up imp edance is nominally 120 k ? with a minimum of 90 k ? and a maximum of 190 k ? . symbol type name and function smbclk i/o smb clock. the smb clock signal is an open drai n signal for serial smb interface. smbdata i/o smb data. the smb data signal is an open drain signal for serial smb interface. smbalrt # o smb alert. the smb alert signal is open drai n for serial smb interface. symbol type name and function ee_di o eeprom data input. the eeprom data input pin is used for output to the memory device. ee_do i eeprom data output. the eeprom data output pin is used for input from the memory device. the ee_do includes an internal pull-up resistor. ee_cs o eeprom chip select. the eeprom chip select signal is used to enable the device. ee_sk o eeprom serial clock. the eeprom shift clock provides the clock rate for the eeprom interface, which is approximately 1 mhz.
networking silicon ? 82546gb datasheet 13 3.4 flash interface signals 3.5 miscellaneous signals 3.5.1 led signals 3.5.2 software definable signals symbol type name and function fl_addr [18:0] o flash address output. the flash address output signals are used for a flash or boot rom device. fl_cs# o flash chip select. the flash chip select signal is used to enable the flash or boot rom device. fl_oe# o flash output enable. the flash output enable signal is used to enable the flash buffers. fl_we# o flash write enable output. the flash write enable output signals are used for write cycles. fl_data [7:2] ts flash data i/o. the flash data i/o signals are bi-d irectional and used for flash data. these signals include inte rnal pull-up devices. fl_data [1:0]/ lan_disa ble# ts flash data i/o [1:0] / lan port disable. these pins are inputs from the flash memory. alternatively, they can be used to disable the lan a or lan b port from a system super i/o general (gp) port. (fl_data[1] corresponds to lan b, and fl_data[0], to lan a.) they have internal pull-up devices. if the 82546gb is not using flash functionality, these pins should be connected to external pull-up resistors. if the pins are used as lan_disable#, the device transitions to a low power state, and the corresponding lan port is disabled when it s pin is sampled low on the rising edge of pci reset. symbol type name and function led1/act# o activity. programmable led indication. defaults to flash to indicate transmit or receive activity. led0/link# o link. programmable led indication. defaults to indicate link connectivity. led2/link100# o link100. programmable led indication. defaults to indicate link at 100 mbps. led3/link1000# o link1000. programmable led indication. defaults to indicate link at 1000 mbps. symbol type name and function sdp[7:6] sdp[1:0] ts software defined pin. the software defined pins are reserved and programmable with respect to input and output capability. these default to input signals upon power- up but may be configured differently by the eeprom. the upper four bits may be mapped to the general purpose interrupt bits if they are configured as input signals. note: sdp5 is not included in the group of software defined pins.
82546gb ? networking silicon 14 datasheet 3.6 phy signals 3.6.1 crystal signals 3.6.2 phy analog signals symbol type name and function xtal1 i crystal one. the crystal one pin is a 25 mhz +/- 30 ppm input signal. it can be connected to either an oscillator or crystal. if a crystal is used, crystal two (xtal2) must also be connected. xtal2 o crystal two. crystal two is the output of an internal oscillator circui t used to drive a crystal into oscillation. if an external oscillator is used in the design, xtal2 must be disconnected. symbol type name and function ref_a p reference a. this reference signal should be connected to vss through an external 2.49 k ? resistor. mdia[0]+/- a media dependent interface a [0]. 1000base-t : in mdi configuration, mdia[0]+/- corresponds to bi_da+/-, and in mdi-x configuration, mdia[0]+/- corresponds to bi_db+/-. 100base-tx : in mdi configuration, mdia[0]+/- is used for the transmit pair, and in mdi- x configuration, mdia[0]+/- is used for the receive pair. 10base-t : in mdi configuration, mdia[0]+/- is used for the transmit pair, and in mdi-x configuration, mdia[0]+/- is used for the receive pair. mdia[1]+/- a media dependent interface a [1]. 1000base-t : in mdi configuration, mdia[1]+/- corresponds to bi_db+/-, and in mdi-x configuration, mdia[1]+/- corresponds to bi_da+/-. 100base-tx : in mdi configuration, mdia[1]+/- is used for the receive pair, and in mdi-x configuration, mdia[1]+/- is used for the transit pair. 10base-t : in mdi configuration, mdia[1]+/- is used for the receive pair, and in mdi-x configuration, mdia[1]+/- is used for the transit pair. mdia[2]+/- a media dependent interface a [2]. 1000base-t : in mdi configuration, mdia[2]+/- corresponds to bi_dc+/-, and in mdi-x configuration, mdia[2]+/- corresponds to bi_dd+/-. 100base-tx : unused. 10base-t : unused. mdia[3]+/- a media dependent interface a [3]. 1000base-t : in mdi configuration, mdia[3]+/- corresponds to bi_dd+/-, and in mdi-x configuration, mdia[3]+/- corresponds to bi_dc+/-. 100base-tx : unused. 10base-t : unused. ref_b p reference b. this reference signal should be connected to vss through an external 2.49 k ? resistor.
networking silicon ? 82546gb datasheet 15 3.7 serializer / deserializer signals mdib[0]+/- a media dependent interface b [0]. 1000base-t : in mdi configuration, mdib[0]+/- corresponds to bi_da+/-, and in mdi-x configuration, mdib[0]+/- corresponds to bi_db+/-. 100base-tx : in mdi configuration, mdib[0]+/- is used for the transmit pair, and in mdi- x configuration, mdib[0]+/- is used for the receive pair. 10base-t : in mdi configuration, mdib[0]+/- is used for the transmit pair, and in mdi-x configuration, mdib[0]+/- is used for the receive pair. mdib[1]+/- a media dependent interface b [1]. 1000base-t : in mdi configuration, mdib[1]+/- corresponds to bi_db+/-, and in mdi-x configuration, mdib[1]+/- corresponds to bi_da+/-. 100base-tx : in mdi configuration, mdib[1]+/- is used for the receive pair, and in mdi-x configuration, mdib[1]+/- is used for the transit pair. 10base-t : in mdi configuration, mdib[1]+/- is used for the receive pair, and in mdi-x configuration, mdib[1]+/- is used for the transit pair. mdib[2]+/- a media dependent interface b [2]. 1000base-t : in mdi configuration, mdib[2]+/- corresponds to bi_dc+/-, and in mdi-x configuration, mdib[2]+/- corresponds to bi_dd+/-. 100base-tx : unused. 10base-t : unused. mdib[3]+/- a media dependent interface b [3]. 1000base-t : in mdi configuration, mdib[3]+/- corresponds to bi_dd+/-, and in mdi-x configuration, mdib[3]+/- corresponds to bi_dc+/-. 100base-tx : unused. 10base-t : unused. symbol type name and function rxa+/- rxb +/- i serdes receive pairs a and b. these signals make the differential receive pair for the 1.25 ghz serial interface. if the serd es interface is not used, these pins should not be connected. txa+/- txb +/- o serdes transmit pairs a and b. these signals make the differential transmit pair for the 1.25 ghz serial interface. if the serd es interface is not used, these pins should not be connected. sig_ detect (a and b) i signal detects a and b. these pins indicate whether the serdes signals (connected to the 1.25 ghz serial interf ace) have been detected by the optical transceivers. if the serdes interface is not used, the sig_detect inputs should be connected to ground usi ng pull-down resistors. symbol type name and function
82546gb ? networking silicon 16 datasheet 3.8 jtag test interface signals 3.9 power supply connections 3.9.1 power support signals 3.9.2 digital supplies 3.9.3 analog supplies symbol type name and function jtag_tck i jtag clock. jtag_tdi i jtag tdi. jtag_tdo o jtag tdo. jtag_tms i jtag tms. jtag_ trst# i jtag reset. this is an active low reset signal for jtag. this signal should be terminated using a pull-down resistor to ground. it must not be left unconnected. clk_view o clock view. the clock view signal is an output of clock signals required for ieee testing. test# i factory test pin. this is an active low input and has an internal pull-up resistor. for normal operation, test# should be left unconnected. symbol type name and function ctrl_15 o 1.5 v control. the 1.5 v control signal is an output to an external power transistor. if regulators are used, it should be left unconnected. ctrl_25a o 2.5 v control. the 2.5 v control signal is an output to an external power transistor. if regulators are used, it should be left unconnected. ctrl_25b o 2.5 v control. the 2.5 v control signal is an output to an external power transistor. if regulators are used, it should be left unconnected. symbol type name and function vddo p 3.3 v i/o power supply. dvdd p 1.5 v digital core power supply. symbol type name and function avddh p 3.3 v analog power supply. avddla p 2.5 v analog power supply to port a. avddlb p 2.5 v analog power supply to port b.
networking silicon ? 82546gb datasheet 17 3.9.4 ground and no connects symbol type name and function gnd p ground. nc p no connect. do not connect any circuitry to these pins. pull-up or pull-down resistors should not be connected to these pins. reserved r reserved. these pins are reserved for factory purposes and should be left unconnected. (however, the following pins should be pulled down to ground: a20, b18, and m5. in addition, the following pins should be pulled down to ground through a 1 k ? pull-down resistor: a6, e7 and r1.)
82546gb ? networking silicon 18 datasheet 4.0 test port functionality 4.1 xor testing a common board or system-level manufacturing test for proper electrical continuity between a silicon component and the board is some type of cascaded-xor or nand tree test. the 82546gb implements an xo r tree spanning most i/o signals. the co mponent xor tree consists of a series of cascaded xor logic gates, each stage feeding in the electrical value from a unique pin. the output of the final stage of the tree is visible on an output pin from the component. figure 2. xor tree concept by connecting to a set of test-points or bed-of-na ils fixture, a manufacturing test fixture can test connectivity to each of the compon ent pins included in the tree by sequentially testing each pin, testing each pin when driven bo th high and low, and observing the output of the tree for the expected signal va lue and/or change. 4.1.1 xor tree control and operation the following signals are required to place the 82546gb in xor tree test mode: test function/ mode pin name test_dm_n ewrap clk_byp_n clk_view sdp_b[7] dual-mode name test_ mode[3] test_ mode[2] test_ mode[1] test_ mode[0] xor tree te s t 00000
networking silicon ? 82546gb datasheet 19 i/o pins with dual-mode function for xor test: when xor tree test is selected, th e following pin behavior(s) occur: ? output drivers for the pins listed as tested are all placed in high-impedan ce (tri-state) state to ensure that the board/system test fixture can drive the tested inputs without contention ? the output driver for the xor tree output on pin flsh_ce_n is explicitly enabled. 4.1.2 pins tested when performing xor test, those pins tested by the xor tree all function as inputs, regardless of the normal directionality of the pin. the following table(s) cites the pins tested and not-testable as inputs to the xor tree. table entries do not reflect the natural order of input into the xor tree itself (nor need to, as the output of a mu lti-input xor function is order-independent). pins included in xor test tree are listed in table 1 : table 1. tested pins included in xor tree pin name dual-mode name pin function flsh_ce_n xor_out output of xor tree. pin name pin name pin name pci_ad[63:0] m66en rx_data[7:0] pci_cbe_n[7:0] pci_rst_n rbc0/rx_clk pci_par lan_pwr_good rbc1/mtx_clk pci_par64 pci_serr_n ee_di pci_frame_n pci_perr_n ee_do pci_irdy_n pci_pme_n ee_cs pci_trdy_n aux_pwr ee_sk pci_stop_n smbclk flsh_addr[18:0] pci_idsel smbdat flsh_oe_n pci_devsel_n tx_data[9]/tx_er flsh_we_n pci_req64_n tx_data[8]/tx_en flsh_data[7:0] pci_ack64_n tx_data[7:0] led_a[3:0] pci_req_n gtx_clk led_b[3:0] pci_gnt_n col sdp_a[7,6,1,0] pci_lock_n crs sdp_b[6,1,0] pci_inta_n link/los altclk_125 pci_intb_n rx_data[9]/rx_er pci_clk rx_data[8]/rx_dv
82546gb ? networking silicon 20 datasheet pins not included in xor test tree: ? jtag (tap) interface: trst_n , tck, tdo, tms, and tdo ? test mode decode controls test_dm_n, ewrap, clk_byp_n, clk_view, and sdp_b[7] ? each internal phy's analog signals incl uding phyref, mdi +/-, and phy_hsdacp/n ? pci impedance compensation zpcomp and zncomp ? oscillator signals xtal1 and xtal2 ? test signals includ ing phy_tstpt and each phy's hsdacp/n ? power-control pins ctrl_15, ctrl_25_a, and ctrl_25_b ? smb_alert_n/pci_pwr_good 4.2 tristate mode the 82546gb's tristate test mode is used to explicitly disable output drivers and place outputs in high-impedance (tristate) state. to more readil y support xor or nand-tree like testing of other system components, the 82546gb decodes this test mode from the same signal pins used to exercise xor tree testing. the 82546gb additionall y supports a mechanism to enter tristate mode via the ieee 802.3 jtag (tap) controller. 4.2.1 tristate mode control and operation the following signals are required to pl ace the 82546gb in tristate test mode: when in tristate test mode: ? all output drivers for all digital signal pins are disabled (with the exception of the tdo pin). ? analog signals such as mdi+/-, analog test points, and regulator controls are unaffected. 4.2.2 tristate mode using jtag (tap) the 82546gb can also be placed in tristate mode using the jtag interface and the highz instruction. the highz instruction is used to place the 82546gb in high-impedan ce (tristate) mode, where all digital signal outputs are placed in high-impedance (tri-s tate) output state. test function/ mode pin name test_dm_n ewrap clk_byp_n clk_view sdp_b[7] dual-mode name test_ mode[3] test_ mode[2] test_ mode[1] test_ mode[0] tristate mode 00101
networking silicon ? 82546gb datasheet 21 5.0 voltage, temperature, and timing specifications note: the specification values listed in this section are subject to change without notice. verify with your local intel sales office that you have the latest information before finalizing a design. 5.1 targeted absolu te maximum ratings 5.2 recommended operating conditions table 2. absolute maximum ratings a a. maximum ratings are referenced to ground (vss). permanent device damage is likely to occur if the ratings in this table are exceeded. these values should not be used as the limits for normal device operations. symbol parameter min max unit vdd (3.3) dc supply voltage on vddd or avddh with respect to vss vss - 0.5 4.6 v vdd (2.5) dc supply voltage on avddl with respect to vss vss - 0.5 4.6 or vdd (2.5) + 0.5 b b. the maximum value is the lesser value of 4.6 v or vdd(2.5) + 0.5 v. this specification applies to biasing the device to a ste ady state for an indefinite duration. v vdd (1.5) dc supply voltage on dvdd with respect to vss vss - 0.5 4.6 or vdd (1.5) + 0.5 c c. the maximum value is the lesser value of 4.6 v or vdd(2.5) + 0.5 v. v vdd dc supply voltage vss - 0.5 4.6 v vi / vo lvttl input voltage vss - 0.5 4.6 v vi / vo 5 v compatible input voltage vss - 0.5 6.6 v io dc output current (by cell type): iol = 3 ma iol = 6 ma iol - 12 ma 10 20 40 ma tstg storage temperature range -40 125 c esd per mil_std-883 test method 3015, specification 2001v latchup over/undershoot: 150 ma, 125 c vdd overstress: vdd(3.3)(7.2 v) v table 3. recommended operating conditions a symbol parameter min max unit vdd (3.3) dc supply voltage on vddd or avddh b 3.0 3.6 v vdd (2.5) dc supply voltage on avddl c 2.38 2.62 v vdd (1.5) dc supply voltage on dvdd 1.43 1.57 v vio pci bus voltage reference 3.0 5.25 v
82546gb ? networking silicon 22 datasheet 5.3 dc specifications tr / tf input rise/fall time (normal input) 0 200 ns tr/tf input rise/fall time (schmitt input) 0 10 ms ta operating temperature range (ambient) d 055c tj junction temperature ? 125 c a. sustained operation of the device at conditions exceeding thes e values, even if they are within the absolute maximum rating limits, might result in permanent damage. b. it is recommended for vddo to equal avddh (vddo = avddh) during power-up and normal operation. c. it is recommended for both vddo and avddh to be of a value greater than avddl, with a value greater than dvdd, during power-up (vddo or avddh > avddl > dvdd). d. a higher operating temperature of up to 70 c can be achieved using an appropriate thermal management device. table 4. dc characteristics symbol parameter min typ max units vdd (3.3) dc supply voltage on vddo or avddh 3.00 3.3 3.60 v vdd (2.5) dc supply voltage on avddl 2.38 2.5 2.62 v vdd (1.5) dc supply voltage on dvdd 1.43 1.5 1.57 v table 5.a power supply characteristics d0a (both ports) unplugged/no link 10 mbps operation 100 mbps operation 1000 mbps operation typ icc (ma) max icc (ma) typ icc (ma) max icc (ma) typ icc (ma) max icc (ma) typ icc (ma) max icc (ma) 3.3 v 65 85 100 110 115 120 240 265 2.5 v 60 65 80 80 130 135 310 335 1.5 v 180 190 160 170 200 220 740 840 to ta l device power 650 mw 800 mw 1.0 w 2.7 w 3.2 w table 3. recommended operating conditions a symbol parameter min max unit
networking silicon ? 82546gb datasheet 23 table 5.b 82546gb dual port ethernet controller only d3cold - wake up enabled (both ports) d3cold - wake up disabled (both ports) unplugged/no link 10 mbps operation 100 mbps operation typ icc (ma) max icc (ma) typ icc (ma) max icc (ma) typ icc (ma) max icc (ma) typ icc (ma) max icc (ma) 3.3 v 65 75 100 110 95 120 65 75 2.5 v 65 70 65 70 125 140 60 65 1.5 v 50 50 60 70 105 130 20 40 to ta l device power 450 mw 600 mw 800 mw 400 mw table 5.c 82546gb dual port ethernet controller only uninitialized/disabled d(n) uninitialized (lan pwr good = 0) disabled (via flash address) typ icc (ma) max icc (ma) typ icc (ma) max icc (ma) 3.3 v 75 80 50 55 2.5 v 100 120 50 60 1.5 v 360 385 20 25 to ta l device power 1.0 w 325 mw table 5.d complete subsystem (including the 82546gb) complete subsystem (including 82546gb, magnetics, led, and regulator circuits) d3cold / wake disabled d3cold / wake enabled at 10 mbps d3cold / wake enabled at 100 mbps d0 at 1000 mbps typ icc (ma) max icc (ma) typ icc (ma) max icc (ma) typ icc (ma) max icc (ma) typ icc (ma) max icc (ma) 3.3 v 65 75 110 120 115 140 250 275 2.5 v 60 65 85 90 175 190 500 525 1.5 v 20 40 60 70 105 130 740 840 subsystem to ta l p o w e r mw mw mw mw mw mw mw mw
82546gb ? networking silicon 24 datasheet table 5.e 82546gb serdes design 82546gb only d0a (serdes active) d3cold wake disabled (serdes off) typ icc (ma) max icc (ma) typ icc (ma) max icc (ma) 3.3 v 110 135 85 95 2.5 v 120 125 leakage leakage 1.5 v 170 240 15 20 to ta l device power 900 mw 1.2 w 300 mw 375 mw table 5.f complete subsystem (serdes design - includes the 82546gb) complete subsystem (serdes design) including led and regulator circuits (no optics) d3cold wake disabled (auxiliary power) d0 serdes active (primary power) typ icc (ma) max icc (ma) typ icc (ma) max icc (ma) 3.3 v 85 95 110 135 2.5 ~0 ~0 120 125 1.5 v 15 20 170 240 subsystem 3.3 v current 115 ma 500 ma table 6. i/o characteristics symbol parameter condition min typ max unit v il voltage input low -0.5 0.8 v v ih voltage input high 2.0 v dd +0.3 v v ol voltage output low 0.4 v v oh voltage output high 2.4 v v sh schmitt trigger hysteresis 0.1 v i ol a output current low 3ma drivers (ttl3) 6ma drivers (ttl6) 12ma drivers (ttl12) v ol v ol v ol 3 6 12 ma ma ma
networking silicon ? 82546gb datasheet 25 5.4 ac characteristics i oh a output current high 3ma drivers (ttl3) 6ma drivers (ttl6) 12ma drivers (ttl12) v oh v oh v oh -3 -6 -12 ma ma ma i in input current ttl inputs inputs with pull-down resistors ttl inputs with pull-up resistors v in = v dd or v ss v in = v dd v in = v ss -10 150 -150 ? 1 10 480 -480 ? a ? a ? a i oz 3-state output leakage current v oh = v dd or v ss -10 ? 110 ? a c in input capacitance any input and bi- directional buffer 2.5 pf c out output capacitance any output buffer 2.0 pf c pud pull-up/down resistor value 7.5 20 k ? a. ttl3 signals include: ee_di, ee_sk, ee_cs, and jtag_tdo. ttl6 signals include: fl_ce#, clk_view, fl_d ata[7:0], fl_addr[18:0], fl_oe#, and fl_we#. ttl12 signals include: act_a#, act_b#, link_a#, link_b#, leda100#, ledb100#, leda1000#, and ledb1000#. table 7. ac characteristics: 3.3 v interfacing symbol parameter min typ max unit fpciclk clock frequency in pci mode 66 mhz fpciclk clock frequency in pci-x mode 66 133 mhz table 8. 25 mhz clock input requirements symbol parameter a a. this parameter applies to an oscillator connected to the crysta l one (xtal1) input. alternatively, a crystal may be connected to xtal1 and xtal2 as the frequency source for the internal oscillator. min typ max unit fi_tx_clk tx_clk_in frequency 25 - 50 ppm 25 25 + 50 ppm mhz table 9. link interface clock requirements symbol parameter min typ max unit fgtx a a. gtx_clk is used externally for test purposes only. gtx_clk frequency 125 mhz table 6. i/o characteristics symbol parameter condition min typ max unit
82546gb ? networking silicon 26 datasheet 5.5 serial interface specifications table 10. eeprom interface clock requirements symbol parameter min typ max unit fsk 1mhz table 11. ac test loads for general output pins symbol signal name value units cl tdo 10 pf cl apm_wakeup, pme#, sdp[7:6], sdp[1:0] 16 pf cl ee_di, ee_sk, fl_addr[18:0], fl_cs#, fl_oe#, fl_we#, fl_data[7:0] 18 pf cl rx_activity, tx_activity, link_up 20 pf figure 3. ac test loads for general output pins table 12. driver characteristics symbol parameter min typ max units v od differential output voltage swing a a. this is the maximum inside dimension of the ey e pattern, measured on high and low data pat- terns with pre-emphasis present. load = 100 ? . 875 1325 mv peak- peak v os output offset voltage 1075 1325 mv delta v od change in v od between 0 and 1 b b. this is defined as an absolute value of amplitude jitter. 25 mv r o differential output impedance 80 120 ? i sa , i sb output current on short to vss 40 ma i sab output current when a and b are shorted 12 ma c l
networking silicon ? 82546gb datasheet 27 5.6 timing specifications 5.6.1 pci/pci-x bus interface 5.6.1.1 pci/pci-x bus interface clock table 13. receiver characteristics symbol parameter min typ max units v id differential input voltage swing 100 2000 mv peak- peak r in differential input impedance 80 120 ? table 14. pci/pci-x bus in terface clock parameters symbol parameter a a. rise and fall times are specified in terms of the edge rate measured in v/ns. this slew rate must be met across the minimum peak-to-peak portion of the clock waveform as shown. pci-x 133 mhz pci-x 66 mhz pci 66mhz pci 33 mhz units min max min max min max min max tcycclk cycle time 7.5201520153030 ns th clk high time 3 6 6 11 ns tl clk low time 3 6 6 11 ns clk slew rate 1.5 4 1.5 4 1.5 4 1 4 v/ns rst# slew rate b b. the minimum rst# slew rate applies only to the rising (de-assertion) edge of the reset signal and ensures that system noise cannot render a monotonic signal to appear bouncing in the switching range. 50 50 50 50 mv/ns figure 4. pci/pci-x clock timing 0.6 vcc 0.2 vcc 0.5 vcc 0.4 vcc 0.3 vcc tcyc th tl 0.4 vcc p-to-p (minimum) 3.3 v clock
82546gb ? networking silicon 28 datasheet 5.6.1.2 pci/pci-x bus interface timing notes: 1. output timing measurements are as shown. 2. req# and gnt# signals are point-to-point and have di fferent output valid delay and input setup times than bussed signals. gnt# has a setup of 10 ns; req# has a setup of 12 ns. all other signals are bussed. 3. input timing measurements are as shown. table 15. pci/pci-x bus interface timing parameters symbol parameter pci-x 133 mhz pci-x 66 mhz pci 66mhz pci 33 mhz units min max min max min max min max tval clk to signal valid delay: bussed signals 0.7 3.8 0.7 3.8 2 6 2 11 ns tval (ptp) clk to signal valid delay: point-to-point signals 0.7 3.8 0.7 3.8 2 6 2 12 ns ton float to active delay 0 0 2 2 ns toff active to float delay 7 7 14 28 ns tsu input setup time to clk: bussed signals 1.2 1.7 3 7 ns tsu (ptp) input setup time to clk: point-to-point signals 1.2 1.7 5 10, 12 ns th input hold time from clk 0.5 0.5 0 0 ns trrsu req64# to rst# setup time 10* tcyc 10* tcyc 10* tcyc 10* tcyc ns trrh rst# to req64# hold time 0000ns table 13. pci bus interface timing measurement conditions symbol parameter pci-x pci 66 mhz 3.3 v unit vth input measurement test voltage (high) 0.6*vcc 0.6*vcc v vtl input measurement test voltage (low) 0.25*vcc 0.2*vcc v vtest output measurement test voltage 0.4*vcc 0.4*vcc v input signal slew rate 1.5 1.5 v/ns
networking silicon ? 82546gb datasheet 29 figure 5. pci bus interface output timing measurement figure 6. pci bus interface input timing measurement conditions figure 7. tval (max) rising edge test load v th v tl v test pci_clk v test v step (3.3v signalling) output delay tri-state output output current ?? leakage current t on t off v th v tl v test pci_clk t su v test input v max v test v tl v th input valid t h 10 pf 25 pin test poin t 1/2 inch max.
82546gb ? networking silicon 30 datasheet 5.6.2 link interface timing 5.6.2.1 link interface rise and fall time figure 8. tval (max) falling edge test load table 16. rise and fall times symbol parameter condition min max unit tr clock rise time 0.8 v to 2.0 v 0.7 ns tf clock fall time 2.0 v to 0.8 v 0.7 ns tr data rise time 0.8 to 2.0 v 0.7 ns tf data fall time 2.0 v to 0.8 v 0.7 ns 10 pf 25 pin test poin t 1/2 inch max. v cc
networking silicon ? 82546gb datasheet 31 5.6.2.2 link interface transmit timing figure 9. link interface rise/fall timing figure 10. transmit interface timing table 17. transmit interface timing symbol parameter min typ max unit tperiod gtx_clk period a tbi mode (1000 mbps) a. gtx_clk should have a 100 ppm tolerance. 8ns tsetup data setup to rising gtx_clk 2.5 ns thold data hold from rising grx_clk 1.0 ns tduty gtx_clk duty cycle 40 60 % 2.0 v 0.8 v t f t r 1.4v tx_clock t su tx_data[9:0] valid data t h t period
82546gb ? networking silicon 32 datasheet 5.6.2.3 link interface receive timing figure 11. receive interface timing table 18. receive interface timing symbol parameter min typ max unit treq rbc0/rbc1 frequency tbi mode (1000 mbps) 62.5 mhz tsetup data setup before rising rbc0/rbc1 2.5 ns thold data hold after rising rbc0/rbc1 1 ns tduty rbc0/rbc1 duty cycle 40 60 % ta-b rbc0/rbc1 skew 7.5 8.5 ns 1.4v rbc1 t su rx_data[9:0] comma code_group t h com_det valid data 0.8v 2.0v rbc0 1.4v t h t su t a-b 0.8v 2.0v
networking silicon ? 82546gb datasheet 33 5.6.3 flash interface figure 12. flash read timing table 19. flash read operation timing symbol parameter min typ max unit tce flash ce# or oe# to read data delay 160 ns tacc flash address setup time 160 ns thold data hold time 0 ns figure 13. flash write timing 0ns 250ns flash ce# flash oe# flash we# flash address [18:0] flash data 0ns 250ns 500ns flash ce# flash oe# flash we# flash address [18:0] flash data
82546gb ? networking silicon 34 datasheet 5.6.4 eeprom interface table 20. flash write operation timing symbol parameter min typ max unit twe flash write pulse width (we#) 160 ns tah flash address hold time 0 ns tds flash data setup time 160 ns table 21. link interface clock requirements symbol parameter min typ max unit tpw ee_sk pulse width tperiod *128 ns table 22. link interface clock requirements symbol parameter a a. the ee_do setup and hold time is a function of the clk cycle time but is referenced to o_ee_sk. min typ max unit tdos ee_do setup time tcyc*2 ns tdoh ee_do hold time 0 ns
networking silicon ? 82546gb datasheet 35 6.0 package and pinout information 6.1 device identification note: the black mark in the lower left corner indicates the location of pin 1. figure 14. 82546gb device identification markings FW82546GB country yyww tnnnnnnnn intel (c)'zz (r) 82546gb product name FW82546GB intel product number (c)?zz copyright information yyww date code tnnnnnnnn lot trace code country country of origin assembly
82546gb ? networking silicon 36 datasheet 6.2 package information the 82546gb device is a 364-lead ball grid array (bga) measuring 21 mm 2 . the package dimensions are detailed in the figures below. the nominal ball pitch is 1 mm. figure 15. 82546gb 364-lead bga ball pad dimensions 0.50 mm +/- 0.05 mm solder mask opening detail area 0.65 mm +/- 0.05 mm pad size
networking silicon ? 82546gb datasheet 37 figure 16. 82546gb mechanical specifications 0.40 2.03 20.80 0.51 1.12 0.50 20.80 18.80 18.80 body edge. between the edge of the solder ball and the 4. there shall be a minimum clearance of 0.25 mm ball diameter, parallel to primary datum c. 3. dimension b is meas ured at the maximum solder 2. primary datum c and seating plane are defined by the spherical crowns of the solder balls. 1. controlling dimension: millimeter. e2 e1 d b c b a 1 -b- d1 11 10 68 7 9 12 13 3 2 4 5 19 18 20 14 16 15 17 v n m l k j h g f r p u t e w y -a- e d d3 d2 detail a' a' a2 o detail b' -c- a1 2 a note: ddd c c eee fff o ddd bbb aaa e3 e e3 e e2 3 c s c s fff eee ab d3 e e1 d2 d c b a2 d1 a a1 symbol 0.748 0.740 0.756 19.00 19.20 0.25 0.10 0.15 15.00 1.0 basic 0.20 0.25 0.004 0.010 0.006 0.039 basic 0.010 0.008 0.591 0.819 0.020 0.044 0.020 0.819 0.740 21.00 19.00 bsc 15.00 19.00 21.20 19.20 21.00 19.00 bsc 0.56 0.60 1.17 21.20 0.61 1.22 0.70 0.748 bsc 0.827 0.748 0.591 0.835 0.756 0.748 bsc 0.827 0.022 0.024 0.046 0.835 0.024 0.048 0.028 min 0.016 0.080 dimension in inch dimension in mm 0.50 2.23 nom min 0.60 2.43 max 0.020 0.088 nom 0.024 0.096 max
82546gb ? networking silicon 38 datasheet 6.3 thermal specifications the 82546gb gigabit ethernet controller is specifi ed for operation when the ambient temperature (ta) is within the range of 0 c to 55 c. th e maximum permitted junction temperature is 125 c. tc (case temperature) is calculated using the equation: tc = ta + p ( ? ja - ? jc ) tj (junction temperature) is calculated using the equation: tj = ta + p ? ja the power consumption (p) is calculated by usin g the typical icc and nominal vcc. the thermal resistances are shown in table 23 . thermal resistances are determined empirically with test devices mo unted on standard thermal test boards. real system designs may have different ch aracteristics due to board thickness, arrangement of ground planes, and proximity of other components. the case temperature measurements should be used to assure that the 82546gb gigabit ethernet controller is operating under recommended conditions. the use of a heat sink devi ce can enhance the overall ? ja of the solution in situations where tolerance of higher overall ambi ent air temperatures is desired. intel does not qualify or recommend any specific heat sink device for use wi th the 82546gb gigabit ethernet controller but can provide a thermal report modeling a generic heat sink device and the ? ja that might be achieved with the use of a heat sink device. refer to the 82546eb/gb gigabit ethernet controller thermal properties with external heat sink application note for more information. table 23. thermal characteristics symbol parameter value at specified airflow (m/s) units 0123 ? ja thermal resistance, junction-to- ambient 17.7 15.6 14.8 14.0 c/watt ? jc thermal resistance, junction-to- case 6.8 6.8 6.8 6.8 c/watt
networking silicon ? 82546gb datasheet 39 6.4 ball mapping diagram note: the 82546gb device uses five categories of vdd connections: vddo (3.3 v), avddh (analog 3.3 v), avddl (analog 2.5 v), and dvdd (1.5 v). 1234567891011121314151617181920 a b c d e f g h j k l m n p r t u v w y
82546gb ? networking silicon 40 datasheet 6.5 pinout information table 24. pci address, data, and control signals signal pin signal pin signal pin pci_ad[0] t14 pci_ad[28] y3 pci_ad[56] t17 pci_ad[1] v14 pci_ad[29] u4 pci_ad[57] u18 pci_ad[2] y15 pci_ad[30] v3 pci_ad[58] v18 pci_ad[3] w14 pci_ad[31] v1 pci_ad[59] u16 pci_ad[4] t13 pci_ad[32] l16 pci_ad[60] v17 pci_ad[5] v13 pci_ad[33] m20 pci_ad[61] w18 pci_ad[6] y14 pci_ad[34] m19 pci_ad[62] y19 pci_ad[7] u12 pci_ad[35] m16 pci_ad[63] t16 pci_ad[8] v12 pci_ad[36] m18 cbe[0]# y13 pci_ad[9] t12 pci_ad[37] m17 cbe[1]# v10 pci_ad[10] w12 pci_ad[38] n20 cbe[2]# t8 pci_ad[11] y12 pci_ad[39] n16 cbe[3]# y4 pci_ad[12] v11 pci_ad[40] p20 cbe[4]# v16 pci_ad[13] t11 pci_ad[41] n18 cbe[5]# y18 pci_ad[14] y11 pci_ad[42] p19 cbe[6]# y17 pci_ad[15] w10 pci_ad[43] p16 cbe[7]# t15 pci_ad[16] u8 pci_ad[44] r20 par u10 pci_ad[17] y7 pci_ad[45] p18 par64 v15 pci_ad[18] y6 pci_ad[46] p17 frame# v8 pci_ad[19] v7 pci_ad[47] t20 irdy# w8 pci_ad[20] t7 pci_ad[48] r16 trdy# y8 pci_ad[21] w6 pci_ad[49] u20 stop# v9 pci_ad[22] y5 pci_ad[50] r18 idsel t6 pci_ad[23] v6 pci_ad[51] t19 devsel# t9 pci_ad[24] u6 pci_ad[52] v20 vio y1 pci_ad[25] v5 pci_ad[53] t18 vio y20 pci_ad[26] w4 pci_ad[54] w20 pci_ad[27] v4 pci_ad[55] v19 table 25. pci arbitration signals signal pin signal pin signal pin req64# u14 req# w2 lock# y9 ack64# w16 gnt# t3
networking silicon ? 82546gb datasheet 41 table 26. interrupt signals signal pin signal pin inta# y2 intb# t1 table 27. system signals signal pin signal pin pciclk u2 pcirst# t5 m66en y16 lan_pwr_good a17 table 28. error reporting signals signal pin signal pin serr# t10 perr# y10 table 29. power management signals signal pin signal pin pme# t4 aux_pwr r3 table 30. impedance compensation signals signal pin signal pin zn_comp t2 zp_comp r5 table 31. smb signals signal pin signal pin signal pin smbclk a14 smbdata a15 smbalrt# a16 table 32. eeprom in terface signals signal pin signal pin ee_di c19 ee_cs c20 ee_do b20 ee_sk d20
82546gb ? networking silicon 42 datasheet table 33. flash interface signals signal pin signal pin signal pin fl_addr[0] f16 fl_addr[10] g17 fl_oe# k18 fl_addr[1] e18 fl_addr[11] g16 fl_we# c17 fl_addr[2] e16 fl_addr[12] b15 fl_data[0] / lan_a_disable h16 fl_addr[3] e15 fl_addr[13] d19 fl_data[1] / lan_b_disable g18 fl_addr[4] e14 fl_addr[14] d18 fl_data[2] j16 fl_addr[5] e13 fl_addr[15] c15 fl_data[3] h18 fl_addr[6] d15 fl_addr[16] d16 fl_data[4] j17 fl_addr[7] b16 fl_addr[17] c18 fl_data[5] j18 fl_addr[8] f17 fl_addr[18] d17 fl_data[6] k17 fl_addr[9] f18 fl_cs# h20 fl_data[7] k16 table 34. led signals signal pin signal pin signal pin act_a# n1 linka1000# n3 linkb100# c14 link_a# m1 act_b# b13 linkb1000# c13 linka100# n4 link_b# a13 table 35. software definable signals signal pin signal pin sdpa[0] g4 sdpb[0] d13 sdpa[1] g5 sdpb[1] b12 sdpa[6] e12 sdpb[6] c12 sdpa[7] e11 sdpb[7] d12 table 36. crystal signals signal pin signal pin xtal1 a3 xtal2 a4 table 37. phy signals signal pin signal pin signal pin ref_a e3 mdia2- d1 mdib1- l1 ref_b l4 mdia2+ d2 mdib1+ k1 mdia0- b1 mdia3- e1 mdib2- j2
networking silicon ? 82546gb datasheet 43 mdia0+ b2 mdia3+ e2 mdib2+ j1 mdia1- c1 mdib0- l3 mdib3- h3 mdia1+ c2 mdib0+ k3 mdib3+ j3 table 38. serializer / deserializer signals signal pin signal pin signal pin rxa+ g19 txa+ f19 sig_detect_a e20 rxa- g20 txa- f20 sig_detect_b l20 rxb+ j19 txb+ k19 rxb- j20 txb- k20 table 39. jtag test interface signals signal pin signal pin signal pin jtag_tck p1 jtag_tms p5 clk_view p3 jtag_tdi p4 jtag_rst# n5 test# a8 jtag_tdo p2 table 40. power support signals signal pin signal pin signal pin ctrl_15 a18 ctrl_25a f2 ctrl_b h5 table 37. phy signals signal pin signal pin signal pin
82546gb ? networking silicon 44 datasheet table 41. digital power signals signal pin signal pin signal pin vddo (3.3v) b8 vddo (3.3v) u7 dvdd (1.5v) h13 vddo (3.3v) b14 vddo (3.3v) - pll u11 dvdd (1.5v) h14 vddo (3.3v) b19 vddo (3.3v) u15 dvdd (1.5v) j7 vddo (3.3v) c10 vddo (3.3v) u19 dvdd (1.5v) j14 vddo (3.3v) c16 vddo (3.3v) w1 dvdd (1.5v) m7 vddo (3.3v) d6 vddo (3.3v) w5 dvdd (1.5v) m14 vddo (3.3v) d11 vddo (3.3v) w9 dvdd (1.5v) n7 vddo (3.3v) e17 vddo (3.3v) w13 dvdd (1.5v) n8 vddo (3.3v) - phy b h4 vddo (3.3v) w17 dvdd (1.5v) n13 vddo (3.3v) h19 dvdd (1.5v) g7 dvdd (1.5v) n14 vddo (3.3v) l17 dvdd (1.5v) g8 dvdd (1.5v) p7 vddo (3.3v) m2 dvdd (1.5v) g9 dvdd (1.5v) p8 vddo (3.3v) n19 dvdd (1.5v) g12 dvdd (1.5v) p9 vddo (3.3v) r4 dvdd (1.5v) g13 dvdd (1.5v) p12 vddo (3.3v) r17 dvdd (1.5v) g14 dvdd (1.5v) p13 vddo (3.3v) u1 dvdd (1.5v) h7 dvdd (1.5v) p14 vddo (3.3v) u3 dvdd (1.5v) h8 table 42. analog power signals signal pin signal pin signal pin avddh (3.3 v) b4 avddla (2.5 v) g1 avddlb (2.5 v) l2 avddh (3.3 v) - phy a f1 avddla (2.5 v) g2 avddlb (2.5 v) l5 avddla (2.5 v) a19 avddla (2.5 v) g3 avddlb (2.5 v) l18
networking silicon ? 82546gb datasheet 45 table 43. grounds and no connect signals signal pin signal pin signal pin gnd a1 gnd k2 gnd n10 gnd a2 gnd k4 gnd n11 gnd a5 gnd k5 gnd n12 gnd a10 gnd k7 gnd n17 gnd b3 gnd k8 gnd p10 gnd b6 gnd k9 gnd p11 gnd b11 gnd k10 gnd r2 gnd b17 gnd k11 gnd r19 gnd c3 gnd k12 gnd u5 gnd d3 gnd k13 gnd u9 gnd d8 gnd k14 gnd u13 gnd d14 gnd l7 gnd u17 gnd e19 gnd l8 gnd v2 gnd f3 gnd l9 gnd w3 gnd g10 gnd l10 gnd w7 gnd g11 gnd l11 gnd w11 gnd h2 gnd l12 gnd w15 gnd h9 gnd l13 gnd w19 gnd h10 gnd l14 nc a11 gnd h11 gnd l19 nc a12 gnd h12 gnd m4 nc f4 gnd h17 gnd m8 nc f5 gnd j8 gnd m9 nc h1 gnd j9 gnd m10 nc j4 gnd j10 gnd m11 nc j5 gnd j11 gnd m12 nc m3 gnd j12 gnd m13 nc n2 gnd j13 gnd n9
82546gb ? networking silicon 46 datasheet table 44. reserved signals signal pin signal pin signal pin reserved[0] d4 reserved[10] e10 reserved[20] a9 reserved[1] d5 reserved[11] b7 reserved[21] c11 reserved[2] c4 reserved[12] a7 reserved[22] b10 reserved[3] e4 reserved[13] c8 reserved[23] c6 reserved[4] c5 reserved[14] e8 reserved[24] a20 reserved[5] e5 reserved[15] e9 reserved[25] b18 reserved[6] b5 reserved[16] d9 reserved[26] m5 reserved[7] e6 reserved[17] c9 reserved[27] e7 reserved[8] d7 reserved[18] b9 reserved[28] a6 reserved[9] c7 reserved[19] d10 reserved[29] r1
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